Design for Manufacturability in Via Programmable Gate Arrays

In the fast-paced semiconductor industry, time to market means everything. Accommodating the shortened design cycles, however, is hampered by the ever-increasing design complexity. In addition, the continual drive to achieve higher performance (speed, area, power) has fueled the introduction of new manufacturing processes. Existing integrated circuit design methodologies, such as standard-cells designs are failing to cope with these conflicting requirements at a cost that is supported by ASIC product volumes. This report introduces a new regular logic fabric, Via Programmable Gate Arrays (VPGAs). By employing a regular structure, the design cycles can be greatly reduced. Moreover, as the technology dimensions continue scaling downward, the product yield at the ramp-up becomes a function of systematic faults. In order to meet the market demands, the new designs will have to focus on the Manufacturability in addition to the performance specifications. This report presents an overview and design corrections for the common failure mechanisms in modem Cu Integrated Circuit processes. Furthermore, an implementation of the CLB with a manufacturability focus is described.